Manufacturing method of semiconductor structure having dielectric layer edge covering circuit carrier

ABSTRACT

A manufacturing method of a semiconductor structure includes at least the following steps. An encapsulated semiconductor die is disposed on a first surface of a circuit carrier to be in electrical contact with the circuit carrier. A second surface of the circuit carrier and an edge of the circuit carrier is protected with a patterned dielectric layer, where the second surface of the circuit carrier is opposite to the first surface, and the edge of the circuit carrier is connected to the second surface. A conductive terminal is formed to penetrate through the patterned dielectric layer to be in electrical contact with the circuit carrier.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. application Ser.No. 16/454,099, filed on Jun. 27, 2019. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic devices. As the demand for shrinking electronic devices hasgrown, a need for smaller and more creative packaging techniques ofsemiconductor dies has emerged. Thus, packages such as wafer levelpackaging (WLP) have begun to be developed. A common requirement for anadvanced electronic circuit is the use of multiple integrated circuitdevices (e.g., semiconductor dies) integrated in a single packagedstructure. As such, the configuration of a three-dimensional (3D)package is developed. In another example, chip on substrate (CoS) orchip-on-wafer-on-substrate (CoWoS) technique is developed. As the amountand complexity of the integrated circuit devices mounted in asemiconductor package increase, the multi-chip package can achieve theconfiguration of a system on a chip (SoC). These new integration typesfor semiconductor structures face challenges relative to performance andreliability issues.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A to FIG. 1H are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductorstructure in accordance with some exemplary embodiments of thedisclosure.

FIG. 3 is a schematic cross-sectional view illustrating an applicationof a semiconductor structure in accordance with some exemplaryembodiments of the disclosure.

FIG. 4A to FIG. 4D are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure.

FIG. 5 is a schematic cross-sectional view illustrating an applicationof a semiconductor structure in accordance with some exemplaryembodiments of the disclosure.

FIG. 6A to FIG. 6C are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure.

FIG. 7 and FIG. 8 are schematic cross-sectional views illustratingdifferent variations in a dashed box A outlined in FIG. 6B in accordancewith some exemplary embodiments of the disclosure.

FIG. 9A to FIG. 9C are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure.

FIG. 10A and FIG. 10B are schematic cross-sectional views of variousstages of manufacturing a semiconductor structure in accordance withsome exemplary embodiments of the disclosure.

FIG. 11 is a schematic cross-sectional view illustrating a semiconductorstructure in accordance with some exemplary embodiments of thedisclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testingstructures may be included to aid in the verification testing of the 3Dpackaging or 3DIC devices. The testing structures may include, forexample, test pads formed in a redistribution layer or on a substratethat allows the testing of the 3D packaging or 3DIC, the use of probesand/or probe cards, and the like. The verification testing may beperformed on intermediate structures as well as the final structure.Additionally, the structures and methods disclosed herein may be used inconjunction with testing methodologies that incorporate intermediateverification of known good dies to increase the yield and decreasecosts.

FIG. 1A to FIG. 1H are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure. Referring to FIG. 1A, aplurality of semiconductor dies 110 are disposed on a circuit substrateW1. For example, the semiconductor dies 110 are formed in a device wafer(not shown), which may include different device regions that aresingulated in subsequent steps to form a plurality of semiconductor dies110. After performing a singulation process to separate individualsemiconductor dies 110 from the device wafer, the semiconductor dies 110are bonded to the circuit substrate W1 through flip-chip (face-to-face)bonding. The aforementioned process may be referred to as achip-on-wafer process.

In some embodiments, the semiconductor die 110 includes a semiconductorsubstrate 112 and a plurality of die connectors 114 distributed on thesemiconductor substrate 112. In some embodiments, the semiconductorsubstrate 112 includes an elementary semiconductor (e.g., silicon orgermanium in a crystalline, a polycrystalline, or an amorphousstructure, etc.), a compound semiconductor (e.g., silicon carbide,gallium arsenide, gallium phosphide, indium phosphide, indium arsenide,and/or indium antimonide, etc.), an alloy semiconductor (e.g.,silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminumindium arsenide (AlInAs), aluminium gallium arsenide (AlGaAs), galliumindium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.),combinations thereof, or other suitable materials. For example, thecompound semiconductor substrate may have a multilayer structure, or thesubstrate may include a multilayer compound semiconductor structure. Insome embodiments, the alloy SiGe is formed over a silicon substrate. Inother embodiments, a SiGe substrate is strained. For example, thesemiconductor substrate 112 includes a plurality of semiconductordevices, such as active devices (e.g., transistors, diodes, etc.) and/orpassive devices (e.g., capacitors, resistors, inductors, etc.), or othersuitable electrical components, formed therein. The semiconductorsubstrate 112 may include circuitry (not shown) formed in afront-end-of-line (FEOL), and an interconnect structure (not shown)formed in a back-end-of-line (BEOL).

In some embodiments, the surface where the die connectors 114 aredistributed may be referred to as the active surface of thesemiconductor die 110. For example, the die connectors 114 are metalpillars, controlled collapse chip connection (C4) bumps, micro bumps,electroless nickel-electroless palladium-immersion gold technique(ENEPIG) formed bumps, ball grid array (BGA) bumps, or the like. In anembodiment, the die connectors 114 are micro bumps made of copper,nickel, tin, gold, silver, palladium, metal alloy, the like, or acombination thereof. In some embodiments, the die connectors 114 aresolder free and have substantially vertical sidewalls.

The semiconductor die 110 may be or may include a logic die (e.g.,central processing unit (CPU), graphics processing unit (GPU),system-on-a-chip (SoC), microcontroller, etc.), a memory die (e.g.,dynamic random access memory (DRAM) die, static random access memory(SRAM) die, etc.), a power management die (e.g., power managementintegrated circuit (PMIC) die), a radio frequency (RF) die, a sensordie, a micro-electro-mechanical-system (MEMS) die, a signal processingdie (e.g., digital signal processing (DSP) die), a front-end die (e.g.,analog front-end (AFE) dies), the like, or a combination thereof. Itshould be appreciated that the number of the semiconductor dies and thefunctions of the semiconductor dies to be encapsulated may depend on thedesign requirements.

Continue to FIG. 1A, the circuit substrate W1 includes a substrate 122having a first surface 122 a and a second surface 122 b opposite to eachother, a plurality of conductive vias 124 embedded in the substrate 122and extending from the first surface 122 a towards the second surface122 b, a circuit layer 126 formed on the first surface 122 a of thesubstrate 122 and electrically coupled to the conductive vias 124, and aplurality of conductive connectors 128 disposed on the circuit layer 126to be in contact with external components (e.g., the semiconductor dies110). For example, the substrate 122 is made of silicon or othersuitable materials such as ceramic, glass, plastic, resin or epoxy. Insome embodiments in which the substrate 122 is made of silicon, theconductive vias 124 are formed by forming recesses (not shown) in thesubstrate 122 and depositing dielectric liner (not shown), barriermaterials (not shown), and conductive materials in the recesses of thesubstrate 122, removing excess materials on the substrate 122. Forexample, the recesses of the substrate 122 are lined with the dielectricliner to laterally separate the conductive vias 124 from the substrate122.

The conductive vias 124 may be formed by using a via-first approach, andmay be formed during the formation of the circuit layer 126.Alternatively, the conductive vias 124 are formed by using a via-lastapproach, and may be formed after the formation of circuit layer 126. Insome embodiments, the circuit layer 126 includes circuit patterns (notshown) embedded in a dielectric layer formed in a back-end-of-line(BEOL), and a plurality of conductive pads 126 a electrically coupled tothe circuit patterns. A material of the conductive pads 126 a mayinclude aluminum, but other suitable conductive materials (e.g., copper)may be used. The conductive connectors 128 may land on the conductivepads 126 a of the circuit layer 126, and the conductive connectors 128are electrically coupled to the conductive vias 124 through the circuitlayer 126. In some embodiments, the circuit substrate W1 is a wafer, andthe processes are performed at a die-to-wafer level. Alternatively, theprocess may be performed at the die-to-die level.

Still referring to FIG. 1A, in some embodiments, the semiconductor dies110 are coupled to the circuit substrate W1 by cap layers. For example,the semiconductor dies 110 includes a cap layer (not shown) formed onthe die connectors 114 and facing towards the circuit substrate W1, andthe circuit substrate W1 may include a cap layer (not shown) formed onthe conductive connectors 128 and facing towards the semiconductor dies110. Alternatively, the cap layer of the semiconductor dies 110 or thecap layer of the circuit substrate W1 is omitted. In some embodiments,the cap layers are formed by initially forming a layer of solder throughmethods such as evaporation, electroplating, printing, solder transfer,ball placement, or the like. For example, once the semiconductor dies110 have been disposed on the circuit substrate W1, a reflow process isperformed to cause the cap layers to be melted to form conductive jointsCJ between each semiconductor die 110 and the circuit substrate W1. Theconductive joints CJ provide attachment and electrical connectionsbetween the semiconductor die 110 and the circuit substrate W1.

Referring to FIG. 1B, an insulating encapsulation 130 is formed on thecircuit substrate W1 to encapsulate the semiconductor dies 110. Theinsulating encapsulation 130 is rigid enough to protect thesemiconductor dies 110. A material of the insulating encapsulation 130may include epoxy resin, molding compound, molding underfill, or othersuitable electrical insulating materials. For example, the insulatingencapsulation 130 is formed by compression molding, transfer molding, orthe like. After forming the insulating encapsulation 130, eachsemiconductor die 110 is surrounded by the insulating encapsulation 130,and two adjacent semiconductor dies 110 may be spatially separated bythe insulating encapsulation 130. In some embodiments, a thinningprocess (e.g., mechanical grinding, chemical mechanical polishing (CMP),etching, or the like) is performed to thin the insulating encapsulation130. For example, the insulating encapsulation 130 is thinned until backsurfaces 110 b of the semiconductor dies 110 are exposed, therebyreducing the overall thickness of the structure. In other embodiments,the back surfaces 110 b of the semiconductor dies 110 may be slightlythinned along with the insulating encapsulation 130 during the thinningprocess. For example, the back surfaces 110 b of the semiconductor dies110 and the top surface 130 t of the insulating encapsulation 130 aresubstantially leveled. Alternatively, the thinning process is omitted,and the back surfaces 110 b of the semiconductor dies 110 are covered bythe insulating encapsulation 130.

Continue to FIG. 1B, in some embodiments, before forming the insulatingencapsulation 130, an underfill layer UF is formed between thesemiconductor dies 110 and the circuit substrate W1. The die connectors114, the conductive joints CJ, and the conductive connectors 128 may besurrounded by the underfill layer UF. For example, the underfillmaterial is dispensed and drawn into the gaps between the activesurfaces of the semiconductor dies 110 and the circuit substrate W1 bycapillary action, and then the underfill material may be cured to formthe underfill layer UF. In some embodiments, when a sufficient amount ofthe underfill material is dispensed, a portion of the underfill layer UFmay climb up to cover the sidewalls of the semiconductor dies 110 toprovide a degree of protection. The underfill layer UF may improve theadhesion between semiconductor dies 110 and the circuit substrate W1 andmay provide a stress relief to prevent the conductive joints CJ fromcracking. Alternatively, the underfill layer UF is omitted. In suchembodiments, the insulating encapsulation 130 may be formed in the gapsbetween the active surfaces of the semiconductor dies 110 and thecircuit substrate W1.

Referring to FIG. 1C, a thinning process (e.g., mechanical grinding,chemical mechanical polishing (CMP), etching, and/or a combinationthereof) is performed on the second surface 122 b of the substrate 122of the circuit substrate W1 to expose the conductive vias 124. In someembodiments, to perform the thinning process on the second surface 122 bof the substrate 122, the structure illustrated in FIG. 1B may beoverturned (e.g., flipped upside down) and then disposed on a temporarycarrier TC. A material of the temporary carrier TC may include glass,metal, ceramic, silicon, plastic, combinations thereof, multi-layersthereof, or other suitable material that can hold and support thestructure during the following processes. For example, the top surface130 t of the insulating encapsulation 130 is attached to the temporarycarrier TC through a de-bonding layer DB. The de-bonding layer DB mayinclude a polymer adhesive layer (e.g., die attach film (DAF)), aultra-violet (UV) cured layer, such as a light-to-heat conversion (LTHC)release coating, ultra-violet (UV) glue, which reduces or loses itsadhesiveness when exposed to a radiation source (e.g., UV light or alaser). Other suitable temporary adhesives may be used. Alternatively,the de-bonding layer DB is omitted.

In an exemplary embodiment, the thinning process includes at least thefollowing steps. A planarizing process (e.g., grinding or CMP) may beperformed to initially expose the conductive vias 124. Subsequently, awet or dry etching process having a high etch-rate selectivity betweenthe material of the dielectric liners and the material of the substrate122 may be performed to recess the substrate 122 so as to leave at leastthe conductive vias 124 protruding from the thinned second surface 122b′ of the substrate 122. In an embodiment, the conductive vias 124 areprotruded about a few microns from the thinned second surface 122 b′ ofthe substrate 122. In some embodiments, the conductive vias 124penetrating through the substrate 122 are referred to as throughinterposer vias (TIV) if the circuit substrate W1 is diced (as shown inFIG. 1E and FIG. 1H).

Referring to FIG. 1D, an isolation layer 140 is formed on the substrate122 to at least laterally cover the conductive vias 124. For example,the isolation layer 140 is a dielectric material, such as SiN, an oxide,SiC, SiON, a polymer, or the like. The isolation layer 140 may be formedby spin-coating, printing, a chemical vapor deposition (CVD), or othersuitable deposition process. In some embodiments, the dielectricmaterial with a sufficient thickness is formed on the thinned secondsurface 122 b′ of the substrate 122 and covers the conductive vias 124protruded from the thinned second surface 122 b′, and then the thinningprocess (e.g., mechanical grinding, CMP, etching, and/or a combinationthereof) is performed on the dielectric material to form the isolationlayer 140 and leave the conductive vias 124 accessibly revealing fromthe isolation layer 140. In some embodiments, the top surface of theisolation layer 140 is substantially leveled with the top surfaces ofthe conductive vias 124. In other embodiments, the conductive vias 124are slightly protruded from the top surface of the isolation layer 140.

Referring to FIG. 1E, a singulation process is performed on the circuitsubstrate W1 to dice the circuit substrate W1 into a plurality ofcircuit carriers 120 according to the predetermined areas (not shown).The predetermined areas may be separated by scribe line regions (i.e.non-functional regions; not shown). For example, the circuit substrateW1 is singulated along scribe lines (not shown) within the scribe lineregions by using laser cutting, dicing blade, etching, a combinationthereof, or the like. In some embodiments, the singulation processincludes cutting through the circuit substrate W1 such that a gap G isformed between two adjacent circuit carriers 120. In some embodiments,the singulation process performing on the circuit substrate W1 isregarded as a pre-cutting process. The pre-cutting process may beperformed to completely cut through the circuit substrate W1. In someembodiments, to ensure the circuit substrate W1 is completely cutthrough, a portion of the insulating encapsulation 130 is removed alongwith the circuit substrate W1 in the pre-cutting process. In suchembodiments, a recess R is formed on the insulating encapsulation 130corresponding to the gap G. In some embodiments, in a top-down view (notshown), a plurality of trenches (i.e. gaps G) are formed surrounding thepredetermined areas in a grid pattern, which may include a group ofmutually parallel trenches arranged perpendicular to another group oftrenches.

In other embodiments, the pre-cutting process is to partially cut thecircuit substrate W1. For example, the circuit substrate W1 is notcompletely diced through and a groove is formed on the circuit substrateW1 at this stage, so that the insulating encapsulation 130 is notrecessed but covered by the circuit substrate W1. The details of suchembodiments will be described later in accompanying with figures. Insome embodiments, the circuit carriers 120 are diced as rectangularshapes with sharp edges and corners. For example, the substrate 122 ofthe circuit carrier 120 has substantially vertical diced sidewalls 122 sconnected to the first surface 122 a and the thinned second surface 122b′. In other embodiments in which the groove is formed on the circuitsubstrate in the pre-cutting process, the circuit carrier includes bevelcuts on edges.

Referring to FIG. 1F, a patterned dielectric layer 150 is formed overthe circuit carriers 120 and wraps the edges and corners of the circuitcarriers 120. For example, a dielectric material is formed over thecircuit carriers 120 and extends along the sidewalls 122 s of thecircuit carrier 120 by spin-coating, chemical vapor deposition (CVD),physical vapor deposition (PVD), or the like. The isolation layer 140 isinterposed between the dielectric material and the substrate 122.Subsequently, a portion of the dielectric material is removed to formthe patterned dielectric layer 150 by lithography (i.e. exposure anddevelopment) and etching processes, a laser drilling process, or othersuitable removal techniques. The dielectric material may be differentfrom the material of the underlying isolation layer 140, so that afterperforming the removal process, the isolation layer 140 is not removedand may remain on the thinned second surface 122 b′ of the substrate122.

In some embodiments, the patterned dielectric layer 150 includes athickness T1 that allows the patterned dielectric layer 150 to act as abuffer for lessening stress on the circuit carriers 120. The patterneddielectric layer 150 may be a multi-layered structure. For example, theaverage thickness of the patterned dielectric layer 150 over the circuitcarrier 120 ranges from about 2 μm to about 50 μm. In some embodiments,a material of the patterned dielectric layer 150 is relatively soft tocushion forces exerted on the corners and edges of the circuit carriers120. For example, the patterned dielectric layer 150 has a Young'smodulus smaller than that of the insulating encapsulation 130. TheYoung's modulus of the patterned dielectric layer 150 may be in a rangefrom about 0.5 GPa to about 10 GPa. The patterned dielectric layer 150may be made of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole(PBO), photosensitive polyimide material, soft organic materials,combinations thereof, or other electrical insulating materials.

In some embodiments in which the insulating encapsulation 130 isrecessed, the patterned dielectric layer 150 coves the edges and cornersof the circuit carriers 120 and extends along the sidewalls 122 s tofill the gap G and the recess R, so that the patterned dielectric layer150 may be in physical contact with the insulating encapsulation 130. Insome embodiments, the patterned dielectric layer 150 includes aplurality of first openings OP1 accessibly revealing at least a portionof the TIVs (i.e. conductive vias) 124 for further electricalconnection. In some embodiments, the width (or diameter) of the firstopening OP1 is greater than the width of the corresponding TIV 124 forbetter reliability and manufacturability. It should be noted that thewidth of the first opening OP1 construe no limitation in the disclosureas long as the TIVs 124 may be accessibly revealed for furtherelectrical connection. In some embodiments, the patterned dielectriclayer 150 further includes at least one second opening OP2 formed asidethe gap G or formed at the periphery of the predetermined area. Forexample, the second opening OP2 serves as an alignment mark for thesubsequently process (e.g., singulation). Alternatively, the secondopening OP2 is omitted.

Referring to FIG. 1G, a plurality of conductive terminals 160 is formedon the patterned dielectric layer 150 and inside the first openings OP1of the patterned dielectric layer 150 to be in physical and electricalcontact with the TIVs 124 of the circuit carriers 120. The conductiveterminals 160 are electrically coupled to the semiconductor dies 110through the circuit carriers 120. In some embodiments, the conductiveterminal 160 includes a first portion 162 and a second portion 164disposed on the first portion 162. For example, conductive materials aredeposited on the patterned dielectric layer 150 and inside the firstopenings OP1 of the patterned dielectric layer 150 and patterned to formthe first portions 162 of the conductive terminals 160. The firstportions 162 may include conductive vias formed in the first openingsOP1, conductive pads formed on the conductive vias, under bumpmetallization (UBM) patterns formed on the conductive pads, etc. The UBMpatterns (not shown) may provide additional adhesion to the conductivepads and increase solderability. Alternatively, the UBM patterns areomitted by directly soldering on the conductive pads.

The second portions 164 of the conductive terminals 160 are formed onthe first portions 162 by, for example, using ball mounting, screenprinting, electroless or electroplating, controlled collapse chipconnection (C4) plating, or other suitable techniques. The conductivematerials of the second portions 164 may include lead based materialsuch as lead-tin compounds or lead free eutectics including tin, copper,silver, nickel, gold, and other lead free materials. In someembodiments, after the second portions 164 are formed on the firstportions 162, a reflow process is performed to reshape the secondportions 164, and each of the second portions 164 are limited by one ofthe first portions 162. In some embodiments, the dimensions and pitchesof the conductive terminals 160 are larger than those of the dieconnectors 114 of the semiconductor dies 110 since the scale of thesemiconductor die 110 is smaller than the following external electricalcomponent (shown in FIG. 3). In some embodiments, the conductiveterminals 160 are referred to as refers to ball grid array (BGA) orcontrolled collapse chip connection (C4) bumps.

Continue to FIG. 1G, a de-bonding process may be performed on thetemporary carrier TC to release the temporary carrier TC from theinsulating encapsulation 130 after forming the conductive terminals 160.For example, external energy (e.g., UV light or a laser) is applied onthe de-bonding layer DB. Alternatively, the removal process of thetemporary carrier TC may include a mechanical peel-off process, agrinding process, an etching process, or the like. A cleaning process isoptionally performed to remove residues of the de-bonding layer DB fromthe top surface 130 t of the insulating encapsulation 130 (along withthe back surfaces 110 b of the semiconductor dies 110, in someembodiments). The cleaning process may be performed by using suitablesolvent, cleaning chemical, or other cleaning techniques.

Referring to FIG. 1G and FIG. 1H, a singulation process may be performedto cut through the patterned dielectric layer 150 and the underlyinginsulating encapsulation 130 within the scribe line regions. Forexample, after removing the temporary carrier TC, the structure may betransferred to be placed on a dicing tape which may holds the structurein place during the singulation process. The singulation processincludes cutting the predetermined areas that the pre-cutting processpreviously cut to separate the predetermined areas into a plurality ofsemiconductor structures 10. For example, a dicing tool (e.g., a sawblade or a laser cutting device) is used to cut through the patterneddielectric layer 150 in the gap G and the underlying insulatingencapsulation 130 along the scribe lines SL. It should be noted that asingle semiconductor die 110 illustrated in FIG. 1H merely serves as anillustrative example, more than one semiconductor die 110 may beencapsulated in the insulating encapsulation 130 to performmulti-functions, and the disclosure is not limited thereto.

As shown in FIG. 1H, after performing the singulation process, thepatterned dielectric layer 150 formed over the circuit carrier 120 wrapsthe edges and corners of the circuit carrier 120 and extends to coverthe sidewalls 122 s of the circuit carrier 120. In some embodiments, thepatterned dielectric layer 150 extends beyond the sidewalls 122 s of thecircuit carrier 120 to have a surface 150 a contacting and interfacingwith the insulating encapsulation 130. The surface 150 a of thepatterned dielectric layer 150 may be located between the top surface130 t of the insulating encapsulation 130 and the interface between thecircuit carrier 120 and the insulating encapsulation 130. Afterperforming the singulation process, the singulated sidewall 150 s of thepatterned dielectric layer 150 may be substantially leveled with thesingulated sidewall 130 s of the insulating encapsulation 130.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductorstructure in accordance with some exemplary embodiments of thedisclosure. Referring to FIG. 2, a semiconductor structure 15 isprovided. The semiconductor structure 15 may be similar to thesemiconductor structure 10 described in FIG. 1H, and like elements aredesignated with the same reference numbers for ease of understanding andthe details thereof are not repeated herein. The difference between thesemiconductor structures 10 and 15 includes the profiles of the circuitcarrier 120′ and the patterned dielectric layer 150′. For example, thesubstrate 122′ of the circuit carrier 120′ include a slanted sidewall SSconnected to the thinned second surface 122 b′ and the first surface 122a. The surface area of the thinned second surface 122 b′ may be greaterthan the surface area of first surface 122 a. The patterned dielectriclayer 150′ may cover the slanted sidewall SS. A portion of the patterneddielectric layer 150′ formed on the top of the slanted sidewall SS(e.g., immediately adjacent to the thinned second surface 122 b′) may bethicker than another portion of the patterned dielectric layer 150′formed on the bottom of the slanted sidewall SS (e.g., immediatelyadjacent to the first surface 122 a).

The forming process of the semiconductor structure 15 may be similar tothe forming process of the semiconductor structure 10, except that thesingulation process performing on the circuit substrate as described inFIG. 1E. After performing the singulation process on the circuitsubstrate to dice the circuit substrate into the circuit carriers 120′,the beveled trench is formed between adjacent circuit carriers 120′ by,for example, using the dicing blade with the corresponding shape to passthrough the circuit substrate. For example, the profile of the beveledtrench may be an inverted trapezoid shape in a cross-section. Thecircuit carriers 120′ is formed with the slanted sidewalls SS which maycorrespond to the profile of the beveled trench. Next, the patterneddielectric layer 150′ is formed over the circuit carriers 120′, whereinthe patterned dielectric layer 150′ fills the beveled trench.Subsequently, the singulation is performed on the patterned dielectriclayer 150′ in the beveled trench and the underlying insulatingencapsulation 130 to form the semiconductor structures 15. The formingprocess of the patterned dielectric layer 150′ and the followingsingulation process may be similar to the processes described in FIG. 1Fand FIG. 1G, so the detailed descriptions are omitted for brevity.

FIG. 3 is a schematic cross-sectional view illustrating an applicationof a semiconductor structure in accordance with some exemplaryembodiments of the disclosure. Like elements are designated with thesame reference numbers for ease of understanding and the details thereofare not repeated herein. Referring to FIG. 3, the semiconductorstructure 10 is mounted on an external electric component C1 to form anelectronic device ED1. The external electric component C1 may be or mayinclude an a package substrate, a printed circuit board (PCB), a motherboard, a system board, and/or other circuit board that is capable ofcarrying integrated circuits. For example, the semiconductor structure10 is in physical and electrical contact with the external electriccomponent C1 through the conductive terminals 160. In some embodiments,a reflow process is performed to complete the mechanical and electricalconnection between the semiconductor structure 10 and the externalelectric component C1 by reflowing the second portions 164 of theconductive terminals 160.

In some embodiments, an underfill layer UF is formed between thesemiconductor structure 10 and the external electric component C1 andsurrounds the conductive terminals 160 to provide adhesion and stressrelief therebetween. The circuit carrier 120 is separated from theunderfill UF by the patterned dielectric layer 150. In certainembodiments in which the patterned dielectric layer 150 is provided withthe second openings OP2, the underfill layer UF is formed in the gapbetween the patterned dielectric layer 150 and the external electriccomponent C1 and extends into the second openings OP2 the patterneddielectric layer 150. After mounting the semiconductor structure 10 ontothe external electric component C1, the semiconductor die 110 is able toreceive and transmit signals from the external electric component C1through the circuit carrier 120 and the conductive terminals 160. Itshould be noted that a single semiconductor structure 10 illustrated inFIG. 3 merely serves as an illustrative example, and the quantity andthe type of the semiconductor structure is not limited to theillustrations.

For example, during the mounting process and/or the followingreliability test, the stack of the semiconductor structure 10 and theexternal electric component C1 is heated and cooled down repeatedly in athermal cycling and/or subjected to shearing and stress. The conductiveterminals 160 and the underfill layer UF near the edges and corners ofthe circuit carrier 120 may suffer from serious stress. The patterneddielectric layer 150 formed on the edges and corners of the circuitcarrier 120 may serve as a stress buffer to absorb and/or disperse thestress between the circuit carrier 120 and the external electriccomponent C1. The occurrence of cracks in the underfill layer UF and/orin the circuit carrier 120, during the mounting process and/or thereliability test, may be prevented, and thus the conductive terminals160 may provide a reliable electrical connection. In some embodiments,significant stress reduction (about 80%) exerted on the corners of thecircuit carrier may be achieved by wrapping the corners of the circuitcarrier with the patterned dielectric layer, compared with the structurewithout the patterned dielectric layer covering the corners of thecircuit carrier.

FIG. 4A to FIG. 4D are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure. Referring to FIG. 4A, apre-cutting process is performed on the circuit substrate W1 (as shownin FIG. 1D) to form a pre-cut circuit substrate W2. The processes priorto the pre-cutting may be similar to the processes described in FIG. 1Ato FIG. 1D, so the detailed descriptions are omitted for brevity. Likeelements are designated with the same reference numbers for ease ofunderstanding and the details thereof are not repeated herein.

The pre-cutting process may include bevel cutting, laser cutting, bladesawing, or the like. In some embodiments, the pre-cutting process is topartially cut the circuit substrate W1 (as shown in FIG. 1D) to form agroove GV thereon. The pre-cutting process does not penetrate thecircuit substrate W1. For example, the pre-cutting process may partiallyremove materials within the scribe line regions, including the isolationlayer 140 and the underlying substrate 122 (as shown in FIG. 1D), toresult in the groove GV. Since a portion of the substrate is removedalong with a portion of the overlying isolation layer, the sidewalls 240s′ of the pre-diced isolation layer 240′ and the sidewalls 222 s′ of thepre-diced substrate 222′ are continuously formed as sidewalls GVs of thegroove GV.

The shape of the groove GV may be defined by the shape of the dicingtool. For example, the dicing tool has a cross-section of a rectangularshape, a triangular shape, a round shape, a polygon shape, a polygonshape with chamfered or beveled endpoint, or the like. In someembodiments, the groove GV is a bevel cut formed by using a V-shapeddicing blade. Alternatively, a beveled groove may be chemically formedalong the predetermined area. For example, the opposing sidewalls GVs ofthe groove GV are slanted towards each other. In some embodiments, thegroove GV reaches a depth D1 of the pre-cut circuit substrate W2. Thedepth D1 may be in a range from about 10 μm to about 150 μm. In someembodiments, the sidewall 222 s′ of the pre-diced substrate 222′ has anangle θ between approximately 5 and 90 degrees relative to the referenceplane 240 t′ which is extended from the top surface of the pre-dicedisolation layer 240′. In other embodiments, the groove GV has a curvedprofile in a cross section. In another embodiment, the V-shaped dicingblade cuts deeper in the pre-cut circuit substrate W2 to render thegroove GV having a V-shaped bottom connected to a vertical sidewall.Alternatively, the groove GV may have a substantially flat bottomconnected to a slanted sidewall by using a different dicing blade. Itshould be noted that FIG. 4A is merely serves as an illustrativeexample, the shape and the depth of the groove GV construe no limitationin the disclosure. In some embodiments, a plurality of grooves GV areformed in a grid pattern in a top-down view (not shown), which mayinclude a group of mutually parallel grooves arranged perpendicular toanother group of grooves.

Referring to FIG. 4B, a first dielectric sub-layer DM1 is formed overthe pre-cut circuit substrate W2. A material of the first dielectricsub-layer DM1 may include polybenzoxazole (PBO), polyimide (PI),benzocyclobutene (BCB), a photo-sensitive resin, but is not limited tothe above-mentioned materials. For example, the first dielectricsub-layer DM1 is formed by spin-coating, dispensing, deposition, orother suitable technique(s). In some embodiments, the first dielectricsub-layer DM1 is conformally formed to cover the pre-diced isolationlayer 240′ and the TIVs 124 of the pre-cut circuit substrate W2. Thesidewalls 240 s′ of the pre-diced isolation layer 240′ and the sidewalls222 s′ of the pre-diced substrate 222′ are in physical contact with thefirst dielectric sub-layer DM1. For example, the groove GV is filled bythe first dielectric sub-layer DM1.

Referring to FIG. 4C, a second dielectric sub-layer DM2 may be formed onthe first dielectric sub-layer DM1, and then patterned to form thepatterned dielectric layer 250. In an exemplary embodiment, the firstdielectric material is deposited and etched back to form the firstdielectric sub-layer DM1 with openings (not shown) exposing theconductive vias 124 of the pre-cut circuit substrate W2. Next, thesecond dielectric material is deposited on the first dielectricsub-layer DM1 and fills the openings of the first dielectric sub-layerDM1, and then portions of the second dielectric sub-layer DM2corresponding to the openings of the first dielectric sub-layer DM1 areremoved to form the second dielectric sub-layer DM2 with openings (notshown). The openings of the first dielectric sub-layer DM1 and thesecond dielectric sub-layer DM2 may accessibly expose the conductivevias 124 of the pre-cut circuit substrate W2 for further electricalconnection. In other embodiments, the first dielectric material and thesecond dielectric material are formed sequentially as blanket layersover the pre-cut circuit substrate W2, and then lithography and etchingprocesses are performed to remove portions of the second dielectricmaterial and the underlying first dielectric material together so as toaccessibly expose the conductive vias 124 of the pre-cut circuitsubstrate W2 for further electrical connection.

In some embodiments, a region of the patterned dielectric layer 250corresponding to the groove GV is slightly recessed relative to otherregion of the patterned dielectric layer 250 as shown in FIG. 4C. Thematerial of the second dielectric sub-layer DM2 may be the same ordifferent from that of the underlying first dielectric sub-layer DM1.For example, the second dielectric sub-layer DM2 is a polymer layer,including benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide (PI),or a solder resist material layer, etc. In some embodiments, the seconddielectric sub-layer DM2 has an electrical insulating material, such asa low-temperature polyimide, different from that of the first dielectricsub-layer DM1. Alternatively, one of the second dielectric sub-layer DM2and the first dielectric sub-layer DM is omitted. It should be notedthat the number of sub-layers illustrated in FIG. 4C merely serves as anillustrative example, more than two sub-layers or a single sub-layer maybe employed as long as the patterned dielectric layer 250 may functionas a buffer that reduces stress exerted on the pre-cut circuit substrateW2.

After forming the patterned dielectric layer 250, the conductiveterminals 160 are formed on the patterned dielectric layer 250 andextend into the openings (not labeled) of the patterned dielectric layer250 to be in physical and electrical contact with the conductive vias124 of the pre-cut circuit substrate W2. The materials and the formingprocess of the conductive terminals 160 may be similar to those of theconductive terminals 160 described in FIG. 1G, so the detaileddescriptions are omitted for brevity. Subsequently, the de-bondingprocess may be performed on the temporary carrier TC to remove thetemporary carrier TC. The de-bonding process is similar to the processdescribed in FIG. 1G, so the detailed descriptions are omitted forbrevity.

Referring to FIG. 4C and FIG. 4D, a singulation process may be performedto cut through the patterned dielectric layer 250, the pre-cut circuitsubstrate W2, and the insulating encapsulation 130 within the scribeline regions. For example, after removing the temporary carrier TC, thestructure may be transferred to be placed on the dicing tape forsingulation. The singulation process includes cutting the predeterminedareas that the pre-cutting process previously cut to separate thepredetermined areas into a plurality of semiconductor structures 20. Thesingulation process may provide a full cut passing through the pre-cutcircuit substrate W2 to render a plurality of circuit carriers 220. Forexample, the dicing tool (not shown) cuts along the scribe lines SL,within the groove GV, so that a portion of the patterned dielectriclayer 250 in the groove GV is remained on the circuit carrier 220. Thecircuit substrate is cut by two-step cutting process (i.e., the pre-cutand the singulation) so that the periphery of the circuit carrier 220has a chamfered profile as shown in FIG. 4D.

In some embodiments, the groove GV, which is a bevel cut, is formed witha width greater than the width of a kerf created by the dicing tool, sothat after singulation, the circuit carrier 220 of the semiconductorstructure 20 includes the beveled edge 220 e, and a substantiallyvertical singulated sidewall 220 s connected to the beveled edge 220 e.The beveled edge 220 e is an edge that is not substantiallyperpendicular to the surfaces (e.g., second surface or sidewall of thesubstrate) connected thereto. In some embodiments, a singulated sidewall250 s of the patterned dielectric layer 250 disposed on the beveled edge220 e is substantially leveled with the singulated sidewall 220 s of thecircuit carrier 220 and the singulated sidewall 130 s of the insulatingencapsulation 130. Due to the existence of the beveled edge 220 e of thecircuit carrier 220 and the patterned dielectric layer 250 covering thebeveled edge 220 e, edge/corner cracking of the circuit carrier 220 maybe eliminated and the reliability of the semiconductor structure 20 isimproved.

FIG. 5 is a schematic cross-sectional view illustrating an applicationof a semiconductor structure in accordance with some exemplaryembodiments of the disclosure. Like elements are designated with thesame reference numbers for ease of understanding and the details thereofare not repeated herein. Referring to FIG. 5, the semiconductorstructure 20 is mounted on the external electric component C1 to form anelectronic device ED2. The semiconductor structure 20 is in physical andelectrical contact with the external electric component C1 through theconductive terminals 160, and the underfill layer UF is optionallyformed between the external electric component C1 and the semiconductorstructure 20 to provide adhesion and stress relief therebetween. Theelectronic device ED2 is similar to the electronic device ED1 describedin FIG. 3, so the detailed descriptions are omitted for brevity. In someembodiments, a sufficient amount of the underfill layer UF is dispensedso that a portion of the underfill layer UF climbs upwardly to cover atleast a portion of the singulated sidewall 250 s of the patterneddielectric layer 250 or extend further to cover at least a portion ofthe singulated sidewall 220 s of the circuit carrier 220 for protection.

FIG. 6A to FIG. 6C are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure. The structure shown in FIG. 6Ais fabricated by the processes similar to the processes described inFIG. 4A and FIG. 4B, for example, the pre-cutting process is performedon the circuit substrate to form the groove, and then the firstdielectric sub-layer is formed over the circuit substrate and fills thegroove. Like elements are designated with the same reference numbers forease of understanding and the details thereof are not repeated herein.Referring to FIG. 6A, a portion of the first dielectric sub-layer isremoved to form the first patterned sub-layer 352 with first recesses R1and a second recess R2 by, for example, using lithography and etchingprocesses or other suitable techniques.

The first recesses R1 of the first patterned sub-layer 352 mayaccessibly reveal at least a portion of the TIVs 124 for furtherelectrical connection. The width (or diameter) of the first recess R1may be wider than the width of the corresponding TIV 124. Alternatively,the width of the first recess R1 is narrower than the width of thecorresponding TIV 124. In some embodiments, a portion of the firstdielectric sub-layer formed in the groove GV is removed to form thesecond recess R2. The width of the groove GV may be greater than thewidth of the second recess R2. For example, the the bottoms of theslanted sidewalls GVs are accessibly exposed by the second recess R2,while the tops of the slanted sidewalls GVs are still covered by thefirst patterned sub-layer 352. It should be noted that the profiles ofthe first recesses R1 and the second recess R2 shown in FIG. 6A aremerely serves as an illustrative example, the profiles of the firstrecesses R1 and the second recess R2 may be tapered or may havesubstantially vertical sidewalls, which depends on the employedformation techniques.

Referring to FIG. 6B, a second patterned sub-layer 354 is optionallyformed on the first patterned sub-layer 352. The forming process and thematerial of the second patterned sub-layer 354 may be similar to thoseof the second dielectric sub-layer DM2 described in FIG. 4C, except thatthe second patterned sub-layer 354 further includes first recesses R1and the second recess R2 respectively corresponding to the firstrecesses R1 and the second recess R2 of the first patterned sub-layer352. The first patterned sub-layer 352 and the second patternedsub-layer 354 may be collectively viewed as the patterned dielectriclayer 350.

In some embodiments, the first recesses R1 and the second recess R2 ofthe second patterned sub-layer 354 are respectively aligned with theunderlying first recesses R1 and the second recess R2 of the firstpatterned sub-layer 354. For example, the width (or diameter) of thefirst recess R1 of the second patterned sub-layer 354 and/or the widthof the second recess R2 of the second patterned sub-layer 354 aresubstantially aligned with the width of the first recess R1 of theunderlying first patterned sub-layer 352 and/or the width of the secondrecess R2 of the underlying first patterned sub-layer 352.Alternatively, as will be described later in other embodiments, thewidth of the first recess of the first and second patterned sub-layersare not aligned and/or the width of the second recess of the first andsecond patterned sub-layers are not aligned. In other embodiments, therecesses of the second patterned sub-layer 354 and the first patternedsub-layer 352 are formed during the same damascene process. It should benoted that the number of sub-layers illustrated in FIG. 6B merely servesas an illustrative example, and the patterned dielectric layer 350 mayinclude more than two sub-layers or a single sub-layer which depends onthe design requirements.

Continue to FIG. 6B, after forming the patterned dielectric layer 350,the conductive terminals 160 are formed on the patterned dielectriclayer 350 and embedded in the patterned dielectric layer 350 to be inphysical and electrical contact with the underlying TIVs 124. Forexample, the bottoms of the conductive terminals 160 formed in the firstrecesses R1 of the first patterned sub-layer 352 and the secondpatterned sub-layer 354. The forming process and the material of theconductive terminals 160 may be similar to those of the conductiveterminals 160 described in FIG. 1G, so the detailed descriptions areomitted for brevity. After forming the conductive terminals 160, thesecond recess R2 may remain unmasked so that the bottoms of the grooveGV are not covered. Subsequently, the de-bonding process may beperformed on the temporary carrier TC to release from the insulatingencapsulation 130. The de-bonding process is similar to the processdescribed in FIG. 1G, so the detailed descriptions are omitted forbrevity.

Referring to FIG. 6B and FIG. 6C, a singulation process may be performedto cut through the pre-cut circuit substrate W2 and the underlyinginsulating encapsulation 130 within the scribe line regions. Thesingulation process includes cutting the predetermined areas that thepre-cutting process previously cut to separate the predetermined areasinto a plurality of semiconductor structures 30. The singulation processmay provide a full cut penetrating through the pre-cut circuit substrateW2 to render a plurality of circuit carriers 220. For example, thedicing tool cuts along the scribe lines SL, within the second recess R2,so that the dicing tool cuts the pre-cut circuit substrate W2 and theunderlying insulating encapsulation 130 without dicing the patterneddielectric layer 350, so that the patterned dielectric layer 350partially covers the beveled edge 220 e of the circuit carrier 220 forprotection, as shown in FIG. 6C. In other embodiments, the sidewalls ofthe patterned dielectric layer 350 in the scribe line region areslightly cut, but at least a portion of the patterned dielectric layer350 remains partially covering the beveled edge 220 e of the circuitcarrier 220 for protection. It should be noted that the coverage of thepatterned dielectric layer 350 to the beveled edge 220 e of the circuitcarrier 220 construes no limitation in the disclosure as long as thepatterned dielectric layer 350 may function as a buffer during thesubsequent mounting or testing process.

FIG. 7 and FIG. 8 are schematic cross-sectional views illustratingdifferent variations in a dashed box A outlined in FIG. 6B in accordancewith some exemplary embodiments of the disclosure. Referring to FIG. 7and FIG. 8, the width RW2 of the second recess R2′ of the secondpatterned sub-layer 354′ is less than the width RW1 of the second recessR2 of the first patterned sub-layer 352. In some embodiments, the secondpatterned sub-layer 354′ covers the inner sidewalls of the firstpatterned sub-layer 352 defining the second recess R2. As shown in FIG.8, the width RW2′ of the second recess R2′ of the second patternedsub-layer 354″ is greater than the width RW1 of the second recess R2 ofthe first patterned sub-layer 352, so that at least a portion of thefirst patterned sub-layer 352 may be exposed by the overlying secondpatterned sub-layer 354″.

It should be noted that the first recess of the first patternedsub-layer and the second patterned sub-layer may have the same orsimilar configuration(s) as illustrated in FIG. 7 and FIG. 8. Themisalignment of the recess of the second patterned sub-layer and therecess of the first patterned sub-layer may result from the overlayerror caused by variations in lithography and etching processes or otherfactors. The overlay error may be within the process variation window,and may not cause reliability issues for the semiconductor structure.

FIG. 9A to FIG. 9C are schematic cross-sectional views of various stagesof manufacturing a semiconductor structure in accordance with someexemplary embodiments of the disclosure. Like elements are designatedwith the same reference numbers for ease of understanding and thedetails thereof are not repeated herein. Referring to FIG. 9A, a firstdielectric material is formed over the circuit substrate W1 (shown inFIG. 1D). For example, the first dielectric material is deposited on theisolation layer 140 and covers the TIVs 124. Next, a pre-cutting processis performed on the first dielectric material and the underlying circuitsubstrate W1 to form the pre-cut dielectric layer DM1′ and the pre-cutcircuit substrate W2. The pre-cutting process is to partially remove thefirst dielectric material and the underlying circuit substrate W1 so asto render the groove GV on the structure as shown in FIG. 9A.

Since a portion of the circuit substrate W1 is removed along with aportion of the overlying first dielectric material during thepre-cutting process, the sidewalls 450 s′ of the pre-cut dielectriclayer DM1′, the sidewalls 240 s′ of the pre-diced isolation layer 240′,and the sidewalls 222 s′ of the pre-diced substrate 222′ arecontinuously formed as sidewalls GVs of the groove GV. The shape of thegroove GV may be defined by the shape of the dicing tool or theformation techniques as mentioned above, the profile of the grooveillustrated in FIG. 9A merely serves as an illustrative example, theprofile of the groove GV construe no limitation in the disclosure.

Referring to FIG. 9B, after performing the pre-cutting process, a seconddielectric material DM2′ is optionally formed on the pre-cut dielectriclayer DM1′ and fills the groove GV. In some embodiments, a region of thesecond dielectric material DM2′ corresponding to the groove GV isslightly recessed relative to other region of the second dielectricmaterial DM2′. A portion of the second dielectric material DM2′ formedin the groove GV may be in physical contact with the sidewalls 450 s′ ofthe pre-cut dielectric layer DM1′, the sidewalls 240 s′ of the pre-dicedisolation layer 240′, and the sidewalls 222 s′ of the pre-dicedsubstrate 222′. Next, portions of the second dielectric material DM2′and the underlying pre-cut dielectric layer DM1′ at the predeterminedlocations may be removed by, for example, using lithography and etchingprocesses or other suitable techniques, to form the patterned dielectriclayer 450 with the openings. The openings of the patterned dielectriclayer 450 may accessibly reveal at least a portion of the underlyingTIVs 124 for further electrical connection.

Subsequently, the conductive terminals 160 are formed on the patterneddielectric layer 450 and fill in the openings of the patterneddielectric layer 450 to be in physical and electrical contact with theTIVs 124. The materials and the forming process of the conductiveterminals 160 may be similar to those of the conductive terminals 160described in FIG. 1G, so the detailed descriptions are omitted forbrevity. Subsequently, a de-bonding process may be performed on thetemporary carrier TC to release from the insulating encapsulation 130.The de-bonding process is similar to the process described in FIG. 1G,so the detailed descriptions are omitted for brevity.

Referring to FIG. 9B and FIG. 9C, a singulation process may be performedto cut through the patterned dielectric layer 450, the pre-cut circuitsubstrate W2, and the insulating encapsulation 130. For example, afterremoving the temporary carrier TC, the structure may be transferred tobe placed on the dicing tape for singulation. The singulation processincludes cutting the predetermined areas that the pre-cutting processpreviously cut to separate the predetermined areas into a plurality ofsemiconductor structures 40. The singulation process may provide a fullcut passing through the pre-cut circuit substrate W2 to render thecircuit carriers 220. For example, the dicing tool cuts along the scribelines SL, within the groove GV, so that a portion of the patterneddielectric layer 450 in the groove GV is remained on the circuit carrier220.

In some embodiments, after singulation, a singulated sidewall 450 s ofthe second dielectric material DM2′ is substantially leveled with thesingulated sidewall 220 s of the circuit carrier 220 and the singulatedsidewall 130 s of the insulating encapsulation 130. In some embodiments,the semiconductor structure 40 includes the second dielectric materialDM2′ of the patterned dielectric layer 450 encapsulating the pre-cutdielectric layer DM1′ and extending to cover the beveled edge 220 e ofthe circuit carrier 220. Due to the existence of the beveled edge 220 eof the circuit carrier 220 and the patterned dielectric layer 450covering the beveled edge 220 e, edge/corner cracking of the circuitcarrier 220 may be eliminated and the reliability of the semiconductorstructure 40 is improved.

FIG. 10A and FIG. 10B are schematic cross-sectional views of variousstages of manufacturing a semiconductor structure in accordance withsome exemplary embodiments of the disclosure. The structure shown inFIG. 10A is fabricated by the processes similar to the processesdescribed in FIG. 9A and FIG. 9B, for example, the pre-cutting processis performed on the first dielectric material and the underlying circuitsubstrate to form the pre-cut dielectric layer and the pre-cut circuitsubstrate, and then the second dielectric material is formed on thepre-cut dielectric layer. Like elements are designated with the samereference numbers for ease of understanding and the details thereof arenot repeated herein. Referring to FIG. 10A, portions of the seconddielectric material and the underlying pre-cut dielectric layer at thepredetermined locations may be removed by, for example, lithography andetching processes or other suitable techniques, to respectively form thefirst patterned sub-layer 552 and the second patterned sub-layer 554.The first patterned sub-layer 552 and the second patterned sub-layer 554may be collectively viewed as the patterned dielectric layer 550.

The patterned dielectric layer 550 may include the first recesses R1accessibly revealing the underlying TIVs 124, and the second recess R2partially exposing the sidewall GVs of the groove GV. The first recessesR1 and the second recess R2 are similar to the first recesses R1 and thesecond recess R2 described in FIG. 6A and FIG. 6B, so the detaileddescriptions are omitted for brevity. After forming the patterneddielectric layer 550, the conductive terminals 160 are formed on thepatterned dielectric layer 550 and fill the first recesses R1 of thepatterned dielectric layer 550 to be in physical and electrical contactwith the TIVs 124. The materials and the forming process of theconductive terminals 160 may be similar to those of the conductiveterminals 160 described in FIG. 1G, so the detailed descriptions areomitted for brevity. Subsequently, the de-bonding process may beperformed on the temporary carrier TC to release the temporary carrierTC from the insulating encapsulation 130. The de-bonding process may besimilar to the process described in FIG. 1G, so the detaileddescriptions are omitted for brevity.

Referring to FIG. 10A and FIG. 10B, a singulation process may beperformed to cut through the pre-cut circuit substrate W2 and theunderlying insulating encapsulation 130. The singulation processincludes cutting the predetermined areas that the pre-cutting processpreviously cut to separate the predetermined areas into a plurality ofsemiconductor structures 50. The singulation process may provide a fullcut passing through the pre-cut circuit substrate W2 to render thecircuit carriers 220. For example, the dicing tool cuts along the scribelines SL, within the second recess R2, so that the dicing tool cuts thepre-cut circuit substrate W2 and the underlying insulating encapsulation130 without dicing the patterned dielectric layer 550. After dicing, aportion of the patterned dielectric layer 550 is remained partiallycovering the beveled edge 220 e of the circuit carrier 220 forprotection, as shown in FIG. 6C. In other embodiments, the sidewalls ofthe patterned dielectric layer 550 in the scribe line region areslightly cut, but the patterned dielectric layer 550 remains partiallycovering the beveled edge 220 e of the circuit carrier 220 forprotection. It should be noted that the coverage of the patterneddielectric layer 550 to the beveled edge 220 e of the circuit carrier220 construe no limitation in the disclosure as long as the patterneddielectric layer 550 may serve as a buffer during the subsequentmounting or testing process.

FIG. 11 is a schematic cross-sectional view illustrating a semiconductorstructure in accordance with some exemplary embodiments of thedisclosure. Referring to FIG. 11, a semiconductor structure 60 isprovided. The semiconductor structure 60 is similar to the semiconductorstructure 20 described in FIG. 4D, and like elements are designated withthe same reference numbers for ease of understanding and the detailsthereof are not repeated herein. The difference between thesemiconductor structures 20 and 60 lies in that the semiconductorstructure 60 further includes a redistribution circuitry 372.

For example, after forming the first dielectric sub-layer DM1 asdescribed in FIG. 4B, a portion of the first dielectric sub-layer DM1 isremoved to form a first patterned sub-layer 352′ with openings (notlabeled) by, for example, using lithography and etching processes orother suitable techniques. The openings of the first patterned sub-layer352′ may accessibly reveal at least a portion of the underlying TIVs124. In some embodiments, the width (or diameter) of the opening may bewider than the width of the corresponding TIV 124. Alternatively, thewidth of the opening of the first patterned sub-layer 352′ is narrowerthan the width of the corresponding TIV 124. Next, a redistributioncircuitry 372 is formed on the first patterned sub-layer 352′ and in theopenings of the first patterned sub-layer 352′ to be in physical andelectrical contact with the TIVs 124. In an exemplary embodiment, theredistribution circuitry 372 is formed by using patterning andmetallization techniques to form conductive vias, conductive pads,conductive lines, or the like. The redistribution circuitry 372 may beformed to remap a layout for the circuit carrier 220. Next, the secondpatterned sub-layer 254 may be formed on the first patterned sub-layer352′ to partially cover the redistribution circuitry 372. For example,the second patterned sub-layer 254 includes openings (not labeled)accessibly exposing at least a portion of the underlying redistributioncircuitry 372 for further electrical connection.

Subsequently, the conductive terminals 160 are formed on the secondpatterned sub-layer 254 and in the openings of the second patternedsub-layer 254 to be in physical and electrical contact with theredistribution circuitry 372. The forming process of the conductiveterminals 160 may be similar to the process described in FIG. 1G, so thedetailed descriptions are omitted for brevity. In some embodiments, theredistribution circuitry 372 and the patterned dielectric layer 350′including first and second patterned dielectric sub-layers 352′ and 354′are collectively referred to as a redistribution layer (RDL). Theredistribution circuitry 372 forms connections, which may runhorizontally and map the conductive terminals 160 to different TIVs 124,to provide flexibility in the formation of conductive terminals 160. Insome embodiments, forming the redistribution circuitry 372 between thecircuit carrier 220 and the conductive terminals 160 allows the layoutof the circuit carrier 220 to expand wider than the given area, so thatthe occurrence of undesired bridging issues due to the finer pitchbetween adjacent conductive terminals may be prevented. It should benoted that combination schemes of the redistribution layer may be formedto include different types of semiconductor structure discussed herein,so that variations thereof may be carried out while still remainingwithin the scope of the claims and disclosure.

According to some embodiments, a manufacturing method of a semiconductorstructure includes at least the following steps. An encapsulatedsemiconductor die is disposed on a first surface of a circuit carrier tobe in electrical contact with the circuit carrier. A second surface ofthe circuit carrier and an edge of the circuit carrier is protected witha patterned dielectric layer, where the second surface of the circuitcarrier is opposite to the first surface, and the edge of the circuitcarrier is connected to the second surface. A conductive terminal isformed penetrating through the patterned dielectric layer to be inelectrical contact with the circuit carrier.

According to some alternative embodiments, a manufacturing method of asemiconductor structure includes at least the following steps. Aplurality of semiconductor dies on a circuit substrate is encapsulatedwith an insulating encapsulation. The circuit substrate is cut to form aplurality of circuit carriers with diced sidewalls. A patterneddielectric layer is formed on the circuit carriers opposite to theinsulating encapsulation, where a portion of the patterned dielectriclayer extends to cover the diced sidewalls of the circuit carriers. Aplurality of conductive terminals s formed on the patterned dielectriclayer to be electrically coupled to the semiconductor dies through thecircuit carriers. A singulation process is performed to at least cutthrough the insulating encapsulation.

According to some alternative embodiments, a manufacturing method of asemiconductor structure includes at least the following steps. Asemiconductor die is encapsulated on a circuit substrate with aninsulating encapsulation. The circuit substrate is cut to form a circuitcarrier, where the circuit carrier comprising a first surface coupled tothe insulating encapsulation and the semiconductor die, a second surfaceopposite to the first surface, a sidewall connected to the first surfaceand the second surface, and an edge between the second surface and thesidewall. A dielectric layer is formed on the second surface circuitcarrier and extends to at least cover the edge of the circuit carrier. Aconductive terminal is formed on the dielectric layer, where theconductive terminal is partially embedded in the dielectric layer to bein contact with the circuit carrier, and the semiconductor die beingelectrically coupled to the conductive terminal through the circuitcarrier.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A manufacturing method of a semiconductorstructure, comprising: disposing an encapsulated semiconductor die on afirst surface of a circuit carrier to be in electrical contact with thecircuit carrier; protecting a second surface of the circuit carrier andan edge of the circuit carrier with a patterned dielectric layer,wherein the second surface of the circuit carrier is opposite to thefirst surface, and the edge of the circuit carrier is connected to thesecond surface; and forming a conductive terminal penetrating throughthe patterned dielectric layer to be in electrical contact with thecircuit carrier.
 2. The manufacturing method as claimed in claim 1,wherein before protecting the second surface and the edge of the circuitcarrier with the patterned dielectric layer, recessing a substrate ofthe circuit carrier to have a conductive via of the circuit carrierprotruded from a thinned second surface of the circuit carrier, andforming an isolation layer on the thinned second surface of the circuitcarrier, wherein at least a portion of the conductive via is accessiblyrevealed by the isolation layer.
 3. The manufacturing method as claimedin claim 1, wherein protecting the second surface and the edge of thecircuit carrier with the patterned dielectric layer comprises: formingthe patterned dielectric layer on the second surface of the circuitcarrier and extending across the edge of the circuit carrier and beyonda sidewall of the circuit carrier connected to the first surface of thecircuit carrier.
 4. The manufacturing method as claimed in claim 3,further comprising: leveling a sidewall of the patterned dielectriclayer and a sidewall of the encapsulated semiconductor die.
 5. Themanufacturing method as claimed in claim 1, wherein the edge of thecircuit carrier is formed as a beveled edge before forming the patterneddielectric layer.
 6. The manufacturing method as claimed in claim 5,wherein protecting the second surface and the edge of the circuitcarrier with the patterned dielectric layer comprises: forming adielectric material on the second surface and the beveled edge of thecircuit carrier; and removing a portion of the dielectric material onthe beveled edge, so that the patterned dielectric layer partiallycovers the beveled edge of the circuit carrier.
 7. A manufacturingmethod of a semiconductor structure, comprising: encapsulating aplurality of semiconductor dies on a circuit substrate with aninsulating encapsulation; cutting the circuit substrate to form aplurality of circuit carriers with diced sidewalls; forming a patterneddielectric layer on the circuit carriers opposite to the insulatingencapsulation, wherein a portion of the patterned dielectric layerextends to cover the diced sidewalls of the circuit carriers; forming aplurality of conductive terminals on the patterned dielectric layer tobe electrically coupled to the semiconductor dies through the circuitcarriers; and performing a singulation process to at least cut throughthe insulating encapsulation.
 8. The manufacturing method as claimed inclaim 7, wherein when cutting the circuit substrate to form the circuitcarriers, the circuit substrate is cut through to form a gap between theadjacent circuit carriers; after forming the patterned dielectric layer,the portion of the patterned dielectric layer is formed in the gapbetween the adjacent circuit carriers; and the singulation processcomprises cutting through the portion of the patterned dielectric layerand the underlying insulating encapsulation.
 9. The manufacturing methodas claimed in claim 7, wherein cutting the circuit substrate comprisesforming a groove on a surface of the circuit substrate opposite to theinsulating encapsulation; and after forming the patterned dielectriclayer, the portion of the patterned dielectric layer is formed in thegroove; and the singulation process comprises cutting within the groove.10. The manufacturing method as claimed in claim 9, wherein thepatterned dielectric layer is formed with a recess corresponding to thegroove, and the recess is formed smaller than the groove.
 11. Themanufacturing method as claimed in claim 10, wherein when performing thesingulation process, the circuit substrate is cut corresponding to therecess of the patterned dielectric layer, so that after performing thesingulation process, a portion of the patterned dielectric layer isremained on the groove.
 12. The manufacturing method as claimed in claim9, wherein a first dielectric material of the patterned dielectric layeris formed on the circuit substrate, and then a portion of the firstdielectric material of the patterned dielectric layer and the underlyingcircuit substrate are removed to form the groove.
 13. The manufacturingmethod as claimed in claim 7, further comprising: forming aredistribution circuitry in the patterned dielectric layer to reroute anelectrical path of the circuit carriers before forming the conductiveterminals.
 14. A manufacturing method of a semiconductor structure,comprising: encapsulating a semiconductor die on a circuit substratewith an insulating encapsulation; cutting the circuit substrate to forma circuit carrier, wherein the circuit carrier comprising a firstsurface coupled to the insulating encapsulation and the semiconductordie, a second surface opposite to the first surface, a sidewallconnected to the first surface and the second surface, and an edgebetween the second surface and the sidewall; forming a dielectric layeron the second surface circuit carrier and extending to at least coverthe edge of the circuit carrier; and forming a conductive terminal onthe dielectric layer, wherein the conductive terminal is partiallyembedded in the dielectric layer to be in contact with the circuitcarrier, and the semiconductor die being electrically coupled to theconductive terminal through the circuit carrier.
 15. The manufacturingmethod as claimed in claim 14, further comprising: forming an isolationlayer on the second surface of the circuit carrier before forming thedielectric layer, wherein the dielectric layer is formed on theisolation layer, and a material of the isolation layer is different fromthat of the dielectric layer.
 16. The manufacturing method as claimed inclaim 14, wherein forming the dielectric layer comprising: extending thedielectric layer beyond the edge of the circuit carrier and along thesidewall of the circuit carrier to be in contact with the insulatingencapsulation.
 17. The manufacturing method as claimed in claim 16,wherein when cutting the circuit substrate, a portion of the insulatingencapsulation is also removed, so that an interface between thedielectric layer and the insulating encapsulation is between the firstsurface of the circuit carrier and a surface of the insulatingencapsulation opposite to the first surface of the circuit carrier. 18.The manufacturing method as claimed in claim 14, wherein cutting thecircuit substrate comprises: performing a bevel cutting process on thecircuit substrate, wherein the edge of the circuit carrier is a bevelcut, and after the dielectric layer is formed, the dielectric layerextends beyond the second surface of the circuit carrier to partiallycover the bevel cut.
 19. The manufacturing method as claimed in claim14, wherein cutting the circuit substrate comprises: performing a bevelcutting process on the circuit substrate, wherein the edge of thecircuit carrier is a bevel cut, and after the dielectric layer isformed, the dielectric layer extends to cover the edge of the circuitcarrier, and a sidewall of the dielectric layer is substantially leveledwith the sidewall of the circuit carrier.
 20. The manufacturing methodas claimed in claim 14, further comprising: forming a redistributioncircuitry on the circuit carrier and in the dielectric layer beforeforming the conductive terminal, wherein after the conductive terminalis formed, the conductive terminal is electrically coupled to thecircuit carrier through the redistribution layer.